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Diode Circuits(8)BJT and MOSFET Amplifiers(18)Op-amp Circuits and Compensation(14)

Diode Circuits

8 Questions

GATE→2026→Analog Circuits→Diode Circuits

Q1

NAT[2 Marks]

Consider the ideal diodes D1 and D2 as shown in the Figure with cut-in voltage $V_{\gamma}=0$ Volt and $v_{i}(t)$ is in Volt. The maximum voltage (Volt) of the output $v_{o}(t)$ is ______ (rounded off to two decimal places)

Explanation

GATE→2025→Analog Circuits→Diode Circuits

Q2

MSQ[2 Marks]

All the diodes in the circuit given below are ideal. Which of the following plots is/are correct when $V_I$ (in Volts) is swept from -M to M?

(A)

(A)

(B)

(B)

(C)

(C)

(D)

(D)

Explanation

GATE→2025→Analog Circuits→Diode Circuits

Q3

NAT[2 Marks]

The diode in the circuit shown below is ideal. The input voltage (in Volts) is given by $V_I = 10 \sin(100\pi t)$, where time t is in seconds. The time duration (in ms, rounded off to two decimal places) for which the diode is forward biased during one period of the input is ______

Explanation

GATE→2024→Analog Circuits→Diode Circuits

Q4

MCQ[1 Mark]

In the circuit shown, the n:1 step-down transformer and the diodes are ideal. If the input voltage (in Volts) is $V_s(t) = 10\sin\omega t$ and the average value of load voltage $V_L(t)$ (in Volts) is $2.5/\pi$, the value of n is

(A)

4

(B)

8

(C)

12

(D)

16

Explanation

GATE→2024→Analog Circuits→Diode Circuits

Q5

NAT[1 Mark]

As shown in the circuit, the initial voltage across the capacitor is 10 V, with the switch being open. The switch is then closed at $t = 0$. The total energy dissipated in the ideal Zener diode ($V_Z = 5$ V) after the switch is closed (in mJ, rounded off to three decimal places) is

Explanation

GATE→2024→Analog Circuits→Diode Circuits

Q6

NAT[2 Marks]

For the two port network shown below, the value of the $Y_{21}$ parameter (in Siemens) is

Explanation

GATE→2023→Analog Circuits→Diode Circuits

Q7

MCQ[2 Marks]

In the circuit shown below, $D_1$ and $D_2$ are silicon diodes with cut-in voltage of 0.7 V. $V_{IN}$ and $V_{OUT}$ are input and output voltages in volts. The transfer characteristic is

(A)

Option A

(B)

Option B

(C)

Option C

(D)

Option D

Explanation

GATE→2022→Analog Circuits→Diode Circuits

Q8

NAT[2 Marks]

A circuit and the characteristics of the diode (D) in it are shown. The ratio of the minimum to the maximum small signal voltage gain $\frac{\partial V_{out}}{\partial V_{in}}$ is _______ (rounded off to two decimal places).

Explanation

BJT and MOSFET Amplifiers

18 Questions

GATE→2026→Analog Circuits→BJT and MOSFET Amplifiers

Q9

MCQ[1 Mark]

Consider the circuit shown in the Figure with $V_{i}=3$ V and $V_{CC}=12~V.$ Assume $V_{BE}=0.7~V$ and $\beta_{dc}=99$ for the BJT. Which of the following options is the correct value of the current $I_{o}$?

(A)

$60~\mu A$

(B)

6 μΑ

(C)

$3~\mu A$

(D)

$30~\mu A$

Explanation

GATE→2026→Analog Circuits→BJT and MOSFET Amplifiers

Q10

MCQ[2 Marks]

A small signal source, $V_{i}(t)=A~cos(10^{5}t)+B~sin(10^{7}t)$ is applied to a BJT circuit as shown in the Figure. Assume zero source resistance, $V_{BE}=0.7~V.$ $\beta_{dc}=99$, Early voltage $=100~V$ and Thermal voltage $=25~mV$. Effect of internal parasitic capacitances of the BJT may be neglected. Which expression is the best approximation of the output voltage $V_{o}(t)$?

(A)

$-9.1[A~cos(10^{5}t)+B~sin(10^{7}t)]$

(B)

$9.1[A~cos(10^{5}t)-B~sin(10^{7}t)]$

(C)

$-190.4[A~cos(10^{5}t)+B~sin(10^{7}t)]$

(D)

$190.4[A~cos(10^{5}t)-B~sin(10^{7}t)]$

Explanation

GATE→2026→Analog Circuits→BJT and MOSFET Amplifiers

Q11

NAT[2 Marks]

An n-channel MOSFET is connected as shown in the Figure. Assume $V_{TH}=1~V$, $V_{DD}=5~V,$ and $\mu C_{ox}(\frac{W}{L})=2~mA~V^{-2}$ and neglect channel length modulation effects. The gate voltage $(V_{G})$ of the n-channel MOSFET (in Volt) is ______ (rounded off to two decimal places)

Explanation

GATE→2025→Analog Circuits→BJT and MOSFET Amplifiers

Q12

MCQ[1 Mark]

A simplified small-signal equivalent circuit of a BJT-based amplifier is given below. The small-signal voltage gain $v_o / v_S$ (in V/V) is

(A)

$\frac{-\beta R_L}{R_S + r_\pi}$

(B)

$\frac{+\beta R_L}{R_S}$

(C)

$\frac{-\beta R_L}{R_S}$

(D)

$\frac{+\beta R_L}{R_S + r_\pi}$

Explanation

GATE→2025→Analog Circuits→BJT and MOSFET Amplifiers

Q13

MCQ[1 Mark]

The ideal BJT in the circuit given below is biased in the active region with a $\beta$ of 100. If $I_B$ is $10~\mu A$, then $V_{CE}$ (in Volts, rounded off to two decimal places) is

(A)

4.95

(B)

3.03

(C)

1.92

(D)

2.50

Explanation

GATE→2025→Analog Circuits→BJT and MOSFET Amplifiers

Q14

MSQ[1 Mark]

Which of the following statements is/are TRUE with respect to ideal MOSFET-based DC-coupled single-stage amplifiers having finite load resistors?

(A)

The common-gate amplifier has an infinite input resistance

(B)

The common-source amplifier has an infinite input resistance

(C)

The input and output voltages of the common-source amplifier are in phase

(D)

The input and output voltages of the common-drain amplifier are in phase

Explanation

GATE→2025→Analog Circuits→BJT and MOSFET Amplifiers

Q15

MCQ[2 Marks]

The identical MOSFETS $M_1$ and $M_2$ in the circuit given below are ideal and biased in the saturation region. $M_1$ and $M_2$ have a transconductance $g_m$ of 5 mS. The input signals (in Volts) are: $V_1 = 2.5 + 0.01 \sin \omega t$, $V_2 = 2.5 - 0.01 \sin \omega t$. The output signal $V_3$ (in Volts) is

(A)

$3 + 0.05 \sin \omega t$

(B)

$3 - 0.1 \sin \omega t$

(C)

$4 + 0.1 \sin \omega t$

(D)

$4 - 0.05 \sin \omega t$

Explanation

GATE→2025→Analog Circuits→BJT and MOSFET Amplifiers

Q16

MCQ[2 Marks]

In the circuit shown, the identical transistors Q1 and Q2 are biased in the active region with $\beta = 120$. The Zener diode is in the breakdown region with $V_Z = 5$ V and $I_Z = 25$ mA. If $I_L = 12$ mA and $V_{EB1} = V_{EB2} = 0.7$ V then the values of $R_1$ and $R_2$ (in $k\Omega$, rounded off to one decimal place) are respectively.

(A)

0.6 and 0.4

(B)

1.4 and 2.5

(C)

14.0 and 25.0

(D)

6.0 and 4.0

Explanation

GATE→2024→Analog Circuits→BJT and MOSFET Amplifiers

Q17

MCQ[1 Mark]

In the circuit below, assume that the long channel NMOS transistor is biased in saturation. The small signal input impedance $Z_{in}(j\omega)$ is

(A)

$\frac{-g_m}{C_1 C_L \omega^2} + \frac{1}{j\omega C_1} + \frac{1}{j\omega C_L}$

(B)

Option B

(C)

Option C

(D)

Option D

Explanation

GATE→2024→Analog Circuits→BJT and MOSFET Amplifiers

Q18

MCQ[1 Mark]

For the closed loop amplifier circuit shown below, the magnitude of open loop low frequency small signal voltage gain is 40. The closed loop low frequency small signal voltage gain $\frac{v_{out}}{v_{in}}$ is

(A)

0.976

(B)

1.000

(C)

1.025

(D)

0.488

Explanation

GATE→2024→Analog Circuits→BJT and MOSFET Amplifiers

Q19

MCQ[2 Marks]

In the circuit shown below, the transistors $M_1$ and $M_2$ are biased in saturation. Assuming that capacitor $C_1$ is a short circuit at signal frequencies, the magnitude of small signal voltage gain $|v_{out}/v_{in}|$ is

(A)

Option A

(B)

Option B

(C)

Option C

(D)

Option D

Explanation

GATE→2023→Analog Circuits→BJT and MOSFET Amplifiers

Q20

MCQ[1 Mark]

In the circuit shown below, $V_1$ and $V_2$ are bias voltages. Based on input and output impedances, the circuit behaves as a

(A)

voltage controlled voltage source.

(B)

voltage controlled current source.

(C)

current controlled voltage source.

(D)

current controlled current source.

Explanation

GATE→2023→Analog Circuits→BJT and MOSFET Amplifiers

Q21

MCQ[2 Marks]

The h-parameters of a two port network are shown below. The condition for the maximum small signal voltage gain $\frac{V_{out}}{V_s}$ is

(A)

Option A

(B)

Option B

(C)

Option C

(D)

Option D

Explanation

GATE→2023→Analog Circuits→BJT and MOSFET Amplifiers

Q22

NAT[2 Marks]

In the circuit below, the voltage $V_L$ is _______ V (rounded off to two decimal places).

Explanation

GATE→2022→Analog Circuits→BJT and MOSFET Amplifiers

Q23

MCQ[1 Mark]

Consider the CMOS circuit shown in the figure. The steady state output voltage $V_0$ is

(A)

equal to 0 V

(B)

more than 2 V

(C)

less than 2 V

(D)

equal to 2 V

Explanation

GATE→2022→Analog Circuits→BJT and MOSFET Amplifiers

Q24

MCQ[1 Mark]

The ideal long channel nMOSFET and pMOSFET devices shown in the circuits have threshold voltages of 1 V and -1 V, respectively... For the applied voltages as shown, the steady state voltages are

(A)

$V_1 = 5~\text{V}, V_2 = 5~\text{V}$

(B)

$V_1 = 5~\text{V}, V_2 = 4~\text{V}$

(C)

$V_1 = 4~\text{V}, V_2 = 5~\text{V}$

(D)

$V_1 = 4~\text{V}, V_2 = -5~\text{V}$

Explanation

GATE→2022→Analog Circuits→BJT and MOSFET Amplifiers

Q25

MCQ[2 Marks]

Consider an ideal long channel MOSFET (enhancement-mode)... For $V_{GS} = [2 - \sin(2t)]$ V and $V_{DS} = 1$ V, the maximum value of the drain-to-source current is

(A)

40 mA

(B)

20 mA

(C)

15 mA

(D)

5 mA

Explanation

GATE→2022→Analog Circuits→BJT and MOSFET Amplifiers

Q26

NAT[2 Marks]

Consider the circuit shown with an ideal long channel nMOSFET... The value of $\frac{v_A}{v_B}$ is _______ (rounded off to one decimal place).

Explanation

Op-amp Circuits and Compensation

14 Questions

GATE→2026→Analog Circuits→Op-amp Circuits and Compensation

Q27

MCQ[1 Mark]

The ideal OP-AMP circuit shown in the Figure produces output voltage $V_{o}=x$ when the Switch, S, is open. Which of the options represents the output voltage when S is closed?

(A)

X

(B)

$\frac{2}{3}x$

(C)

$\frac{3}{4}x$

(D)

$\frac{1}{2}x$

Explanation

GATE→2026→Analog Circuits→Op-amp Circuits and Compensation

Q28

MCQ[2 Marks]

A circuit using an ideal OP-AMP is shown in the Figure. Which of the following options gives the correct value of the current $I_{X}$?

(A)

2.0 mA

(B)

1.5 mA

(C)

3.0 mA

(D)

0 mA

Explanation

GATE→2026→Analog Circuits→Op-amp Circuits and Compensation

Q29

NAT[2 Marks]

Consider an ideal OP-AMP circuit as shown in the Figure. The resistances $R_{1}=R_{2}=R_{3}=R_{4}=50$ ΚΩ. The magnitude of the closed loop gain is ______ (rounded off to two decimal places)

Explanation

GATE→2025→Analog Circuits→Op-amp Circuits and Compensation

Q30

MSQ[1 Mark]

Which of the following statements is/are TRUE with respect to an ideal opamp?

(A)

It has an infinite input resistance

(B)

It has an infinite output resistance

(C)

It has an infinite open-loop differential gain

(D)

It has an infinite open-loop common-mode gain

Explanation

GATE→2025→Analog Circuits→Op-amp Circuits and Compensation

Q31

NAT[1 Mark]

All the components in the bandpass filter given below are ideal. The lower -3 dB frequency of the filter is 1 MHz. The upper -3 dB frequency (in MHz, rounded off to the nearest integer) is ______

Explanation

GATE→2025→Analog Circuits→Op-amp Circuits and Compensation

Q32

NAT[1 Mark]

A 4-bit weighted-resistor DAC with inputs $b_3$, $b_2$, $b_1$, and $b_0$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic '1' and open otherwise. When the input $b_3 b_2 b_1 b_0$ changes from 1110 to 1101, the magnitude of the change in the output voltage $V_O$ (in mV, rounded off to the nearest integer) is ______

Explanation

GATE→2024→Analog Circuits→Op-amp Circuits and Compensation

Q33

MCQ[2 Marks]

The opamps in the circuit shown are ideal, but have saturation voltages of $\pm 10$ V. Which of the following statements is true?

(A)

Option A

(B)

Option B

(C)

Option C

(D)

Option D

Explanation

GATE→2024→Analog Circuits→Op-amp Circuits and Compensation

Q34

MCQ[2 Marks]

In the circuit below, the opamp is ideal. If the circuit is to show sustained oscillations, the respective values of $R_1$ and the corresponding frequency of oscillation are

(A)

$29R$ and $1/(2\pi\sqrt{6}RC)$

(B)

$2R$ and $1/(2\pi RC)$

(C)

$29R$ and $1/(2\pi RC)$

(D)

$2R$ and $1/(2\pi\sqrt{6}RC)$

Explanation

GATE→2023→Analog Circuits→Op-amp Circuits and Compensation

Q35

MCQ[1 Mark]

A cascade of common-source amplifiers in a unity gain feedback configuration oscillates when

(A)

the closed loop gain is less than 1 and the phase shift is less than $180^\circ$.

(B)

the closed loop gain is greater than 1 and the phase shift is less than $180^\circ$.

(C)

the closed loop gain is less than 1 and the phase shift is greater than $180^\circ$.

(D)

the closed loop gain is greater than 1 and the phase shift is greater than $180^\circ$.

Explanation

GATE→2023→Analog Circuits→Op-amp Circuits and Compensation

Q36

MCQ[2 Marks]

The $\frac{V_{OUT}}{V_{IN}}$ of the circuit shown below is

(A)

$-\frac{R_4}{R_3}$

(B)

$\frac{R_4}{R_3}$

(C)

$1 + \frac{R_4}{R_3}$

(D)

$1 - \frac{R_4}{R_3}$

Explanation

GATE→2022→Analog Circuits→Op-amp Circuits and Compensation

Q37

MSQ[1 Mark]

An ideal OPAMP circuit with a sinusoidal input is shown in the figure... Which of the options is/are correct?

(A)

The circuit is a low pass filter.

(B)

The circuit is a high pass filter.

(C)

The 3 dB frequency is $1000~\text{rad/s}$

(D)

The 3 dB frequency is $\frac{1000}{3}~\text{rad/s}$.

Explanation

GATE→2022→Analog Circuits→Op-amp Circuits and Compensation

Q38

MCQ[2 Marks]

For the following circuit with an ideal OPAMP, the difference between the maximum and the minimum values of the capacitor voltage ($V_c$) is

(A)

15 V

(B)

27 V

(C)

13 V

(D)

14 V

Explanation

GATE→2022→Analog Circuits→Op-amp Circuits and Compensation

Q39

MCQ[2 Marks]

A circuit with an ideal OPAMP is shown. The Bode plot for the magnitude (in dB) of the gain transfer function is also provided. The values of R and C are

(A)

$R = 3~\text{k}\Omega, C = 1~\mu\text{F}$

(B)

$C = 3~\mu\text{F}, R = 1~\text{k}\Omega$

(C)

$R = 4~\text{k}\Omega, C = 1~\mu\text{F}$

(D)

$R = 3~\text{k}\Omega, C = 2~\mu\text{F}$

Explanation

GATE→2022→Analog Circuits→Op-amp Circuits and Compensation

Q40

NAT[2 Marks]

Consider the circuit shown with an ideal OPAMP. The output voltage $V_0$ is _______ V (rounded off to two decimal places).

Explanation