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Number Representations and Combinatorial Circuits(14)Sequential Circuits, Data Converters, and Memories(12)Computer Organization(2)

Number Representations and Combinatorial Circuits

14 Questions

GATE→2026→Digital Circuits→Number Representations and Combinatorial Circuits

Q1

MCQ[1 Mark]

In the circuit shown in the Figure, A and B are logic inputs and Y is the logic output. Which of the following logic operations is realized by the circuit?

(A)

NOR

(B)

OR

(C)

XOR

(D)

AND

Explanation

GATE→2026→Digital Circuits→Number Representations and Combinatorial Circuits

Q2

MCQ[2 Marks]

What is the $10^{\prime}s$ complement of (47) 10?

(A)

52

(B)

53

(C)

54

(D)

55

Explanation

GATE→2026→Digital Circuits→Number Representations and Combinatorial Circuits

Q3

MCQ[2 Marks]

A Boolean function, $f(x,y,z)$ with x as MSB and z as LSB is realized by 4:1 multiplexer (MUX) with select lines, $S_{1}$ and $S_{0}$ (S1 is MSB, $S_{0}$ is LSB) and inputs, Io, $I_{1}$, $I_{2}$, $I_{3}$ as shown in the Figure. Which of the following options is the correct expression of $f(x,y,z)$?

(A)

$xz+y$

(B)

$x\overline{y}+z$

(C)

$xy+z$

(D)

$\overline{x}y+\overline{z}$

Explanation

GATE→2026→Digital Circuits→Number Representations and Combinatorial Circuits

Q4

MSQ[2 Marks]

Consider the four-variable Boolean function, $f(w,x,y,z)=\Sigma m(0,2,5,7,8,10,13,14,15)$ with 'w' as MSB and 'z' as LSB. Which of the following expressions is/are the valid form(s) of $f(w,x,y,z)$?

(A)

$\overline{x}\overline{z}+xz+wxy$

(B)

$xz+wxy+w\overline{x}\overline{z}+\overline{w}xy\overline{z}$

(C)

$\overline{x}\overline{z}+wxy+w\overline{x}\overline{z}+\overline{w}xy\overline{z}$

(D)

$\overline{x}\overline{z}+xz+wy\overline{z}$

Explanation

GATE→2025→Digital Circuits→Number Representations and Combinatorial Circuits

Q5

MCQ[1 Mark]

A 3-input majority logic gate has inputs X, Y, and Z. The output F of the gate is logic '1' if two or more of the inputs are logic '1'. The output F is logic '0' if two or more of the inputs are logic '0'. Which one of the following options is a Boolean expression of the output F?

(A)

$XY + YZ + ZX$

(B)

$XYZ$

(C)

$X + Y + Z$

(D)

$\overline{X}\overline{Y}\overline{Z}$

Explanation

GATE→2025→Digital Circuits→Number Representations and Combinatorial Circuits

Q6

MCQ[1 Mark]

A full adder and an XOR gate are used to design a digital circuit with inputs X, Y, and Z, and output F, as shown below. The input Z is connected to the carry-in input of the full adder. If the input Z is set to logic '1', then the circuit functions as ______ with X and Y as inputs.

(A)

an adder

(B)

a subtractor

(C)

a multiplier

(D)

a binary to Gray code converter

Explanation

GATE→2024→Digital Circuits→Number Representations and Combinatorial Circuits

Q7

MCQ[1 Mark]

For the Boolean function $F(A, B, C, D) = \sum m(0, 2, 5, 7, 8, 10, 12, 13, 14, 15)$, the essential prime implicants are

(A)

$BD, \overline{B}\overline{D}$

(B)

$BD, AB$

(C)

$AB, \overline{B}\overline{D}$

(D)

$BD, \overline{B}\overline{D}, AB$

Explanation

GATE→2024→Digital Circuits→Number Representations and Combinatorial Circuits

Q8

MCQ[2 Marks]

A 4-bit priority encoder has inputs $D_3, D_2, D_1,$ and $D_0$ in descending order of priority. The two-bit output AB is generated as 00, 01, 10, and 11 corresponding to inputs $D_3, D_2, D_1,$ and $D_0$, respectively. The Boolean expression of the output bit B is

(A)

$\overline{D_3} D_2$

(B)

$\overline{D_3} D_2 + \overline{D_3} \overline{D_1}$

(C)

$D_3 \overline{D_2} + \overline{D_3} D_1$

(D)

$D_3 \overline{D_1}$

Explanation

GATE→2024→Digital Circuits→Number Representations and Combinatorial Circuits

Q9

MCQ[2 Marks]

The propagation delay of the $2 \times 1$ MUX shown in the circuit is 10 ns. If S is set to 1 then the output Y is

(A)

a square wave of frequency 100 MHz

(B)

a square wave of frequency 50 MHz

(C)

constant at 0

(D)

constant at 1

Explanation

GATE→2023→Digital Circuits→Number Representations and Combinatorial Circuits

Q10

MCQ[1 Mark]

In the circuit shown below, P and Q are the inputs. The logical function realized by the circuit shown below is

(A)

$Y = PQ$

(B)

$Y = P + Q$

(C)

$Y = \overline{PQ}$

(D)

$Y = P \oplus Q$

Explanation

GATE→2023→Digital Circuits→Number Representations and Combinatorial Circuits

Q11

NAT[1 Mark]

For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is

Explanation

GATE→2022→Digital Circuits→Number Representations and Combinatorial Circuits

Q12

MCQ[1 Mark]

Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for $A_0, A_1, A_2,$ and $A_3$ are

(A)

$A_0 = 0, A_1 = 0, A_2 = 1, A_3 = 1$

(B)

$A_0 = 1, A_1 = 0, A_2 = 1, A_3 = 0$

(C)

$A_0 = 0, A_1 = 1, A_2 = 1, A_3 = 0$

(D)

$A_0 = 1, A_1 = 1, A_2 = 0, A_3 = 0$

Explanation

GATE→2022→Digital Circuits→Number Representations and Combinatorial Circuits

Q13

MSQ[1 Mark]

Select the Boolean function(s) equivalent to $x+yz$, where x, y, and z are Boolean variables, and + denotes logical OR operation.

(A)

$x + z + xy$

(B)

$(x+y)(x+z)$

(C)

$x + xy + yz$

(D)

$x + xz + xy$

Explanation

GATE→2022→Digital Circuits→Number Representations and Combinatorial Circuits

Q14

MSQ[2 Marks]

Consider a Boolean gate (D) where the output Y is related to the inputs A and B as, $Y = A + \overline{B}$, where + denotes logical OR operation. The Boolean inputs '0' and '1' are also available separately. Using instances of only D gates and inputs '0' and '1', (select the correct option(s)).

(A)

NAND logic can be implemented

(B)

OR logic cannot be implemented

(C)

NOR logic can be implemented

(D)

AND logic cannot be implemented

Explanation

Sequential Circuits, Data Converters, and Memories

12 Questions

GATE→2026→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q15

MSQ[1 Mark]

A binary ripple counter is designed to count $(0)_{10}$ to $(64)_{10}.$ Which of the following is/are the number of flip-flops required to design the counter?

(A)

6

(B)

7

(C)

4

(D)

5

Explanation

GATE→2026→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q16

NAT[1 Mark]

The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of 10 cycles/second is applied to its clock (C) input. The frequency of the output Q (in cycles/second) is ______ (rounded off to two decimal places)

Explanation

GATE→2026→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q17

MCQ[2 Marks]

A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay. Which of the following options gives the correct binary representation ($b_{7}b_{6}b_{5}b_{4}b_{3}b_{2}b_{1}b_{0}$) of the content of the shift register immediately after the $5^{th}$ clock transition (positive edge)?

(A)

00011111

(B)

10111111

(C)

00111111

(D)

11000011

Explanation

GATE→2025→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q18

MCQ[2 Marks]

A 10-bit analog-to-digital converter (ADC) has a sampling frequency of 1 MHz and a full scale voltage of 3.3 V. For an input sinusoidal signal with frequency 500 kHz, the maximum SNR (in dB, rounded off to two decimal places) and the data rate (in Mbps) at the output of the ADC are respectively.

(A)

61.96 and 10

(B)

61.96 and 5

(C)

33.36 and 10

(D)

33.36 and 5

Explanation

GATE→2025→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q19

MCQ[2 Marks]

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input P0 is set to logic '0' and P1 is set to logic '1' at all times. The timing diagram of the inputs SEL and S are also shown below. The sequence of output Y from time $T_0$ to $T_3$ is

(A)

1011

(B)

0010

(C)

1101

(D)

0100

Explanation

GATE→2025→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q20

NAT[2 Marks]

In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is ______

Explanation

GATE→2024→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q21

MCQ[2 Marks]

The sequence of states $(Q_1 Q_0)$ of the given synchronous sequential circuit is

(A)

$00 \to 10 \to 11 \to 00$

(B)

$11 \to 00 \to 10 \to 01 \to 00$

(C)

$01 \to 10 \to 11 \to 00 \to 01$

(D)

$00 \to 01 \to 10 \to 00$

Explanation

GATE→2024→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q22

MCQ[2 Marks]

A full scale sinusoidal signal is applied to a 10-bit ADC. The fundamental signal component in the ADC output has a normalized power of 1 W, and the total noise and distortion normalized power is $10~\mu\text{W}$. The effective number of bits (rounded off to the nearest integer) of the ADC is

(A)

7

(B)

8

(C)

9

(D)

10

Explanation

GATE→2023→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q23

MCQ[1 Mark]

The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are

(A)

1000, 3

(B)

333.33, 1

(C)

2000, 3

(D)

333.33, 3

Explanation

GATE→2023→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q24

NAT[1 Mark]

The signal-to-noise ratio (SNR) of an ADC with a full-scale sinusoidal input is given to be 61.96 dB. The resolution of the ADC is _______ bits (rounded off to the nearest integer).

Explanation

GATE→2022→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q25

MSQ[1 Mark]

Select the correct statement(s) regarding CMOS implementation of NOT gates.

(A)

Noise Margin High $(NM_H)$ is always equal to the Noise Margin Low $(NM_L)$, irrespective of the sizing of transistors.

(B)

Dynamic power consumption during switching is zero.

(C)

For a logical high input under steady state, the nMOSFET is in the linear regime of operation.

(D)

Mobility of electrons always influences the switching speed of the NOT gate.

Explanation

GATE→2022→Digital Circuits→Sequential Circuits, Data Converters, and Memories

Q26

MCQ[2 Marks]

For the circuit shown, the clock frequency is $f_0$ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop,

(A)

frequency is $f_0/4$ and duty cycle is 50%

(B)

frequency is $f_0/4$ and duty cycle is 25%

(C)

frequency is $f_0/2$ and duty cycle is 50%

(D)

frequency is $f_0$ and duty cycle is 25%

Explanation

Computer Organization

2 Questions

GATE→2026→Digital Circuits→Computer Organization

Q27

MCQ[2 Marks]

The address of the first location of a 256 kilo byte (KB) memory is (2500)н. Choose the correct address of the last location of the memory.

(A)

(2FFF)H

(B)

(124FF)H

(C)

(424FF)H

(D)

(324FF)H

Explanation

GATE→2024→Digital Circuits→Computer Organization

Q28

NAT[1 Mark]

A machine has a 32-bit architecture with 1-word long instructions. It has 24 registers and supports an instruction set of size 40. Each instruction has five distinct fields, namely opcode, two source register identifiers, one destination register identifier, and an immediate value. Assuming that the immediate operand is an unsigned integer, its maximum value is

Explanation