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Analog Circuits, Op-Amps & Filters(17)Digital Logic & Converters(11)

Analog Circuits, Op-Amps & Filters

17 Questions

GATE→2026→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q1

NAT[1 Mark]

In the linear regulator circuit, find the maximum possible efficiency (in %).

Explanation

GATE→2026→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q2

MCQ[2 Marks]

For the op-amp circuit with open-loop gain A_0 = 10^5, find the closed-loop voltage gain.

(A)

-16.67

(B)

-20.00

(C)

-21.00

(D)

-12.67

Explanation

GATE→2025→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q3

MCQ[1 Mark]

Which statement is true about small signal voltage gain of MOSFET single-stage amplifiers?

(A)

Common source and common gate amplifiers are both inverting amplifiers

(B)

Common source and common gate amplifiers are both non-inverting amplifiers

(C)

Common source amplifier is inverting and common gate amplifier is non-inverting amplifier

(D)

Common source amplifier is non-inverting and common gate amplifier is inverting amplifier

Explanation

GATE→2025→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q4

MCQ[1 Mark]

Assuming ideal op-amps, what does the given multi op-amp circuit represent?

(A)

summing amplifier.

(B)

difference amplifier.

(C)

logarithmic amplifier.

(D)

buffer.

Explanation

GATE→2025→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q5

MCQ[2 Marks]

Find the small-signal output impedance of the given cascode/current source transistor circuit.

(A)

2*r_ds

(B)

1/g_m + r_ds

(C)

g_m * r_ds^2 + 2*r_ds

(D)

infinity

Explanation

GATE→2025→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q6

MCQ[2 Marks]

For large R and C values, what is the output voltage waveform for a high-frequency square wave input?

(A)

(A)

(B)

(B)

(C)

(C)

(D)

(D)

Explanation

GATE→2025→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q7

NAT[2 Marks]

Find the voltage gain of the given ideal multi op-amp circuit with 10 kΩ resistors.

Explanation

GATE→2024→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q8

MCQ[2 Marks]

For the BJT biasing circuit with V_CC = 12 V, R_1 = 100 kΩ, R_2 = 50 kΩ, R_C = 2 kΩ, R_E = 1 kΩ, beta = 100, find quiescent V_CE and I_C.

(A)

4.6 V and 2.46 mA

(B)

3.5 V and 2.46 mA

(C)

2.61 V and 3.13 mA

(D)

4.6 V and 3.13 mA

Explanation

GATE→2024→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q9

NAT[2 Marks]

For the given diode circuit with ideal diodes, find the current I through diode D1 in milliamperes.

Explanation

GATE→2024→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q10

NAT[2 Marks]

Calculate the CMRR in dB for the given difference amplifier with resistor values 10.5 kΩ, 101 kΩ, 9.5 kΩ, and 101.5 kΩ.

Explanation

GATE→2023→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q11

MCQ[2 Marks]

For the op-amp clipper/limiter circuit with 5 V Zener and V_in = 10 sin(1000t) V, find the maximum and minimum values of output voltage V_0.

(A)

The maximum and minimum values of the output voltage V_o are +15 V and -10 V, respectively.

(B)

The maximum and minimum values of the output voltage V_o are +5 V and -15 V, respectively.

(C)

The maximum and minimum values of the output voltage V_o are +10 V and -5 V, respectively.

(D)

The maximum and minimum values of the output voltage V_o are +5 V and -10 V, respectively.

Explanation

GATE→2023→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q12

NAT[2 Marks]

For the transistor-Zener regulator circuit with beta = 99 and 5 V Zener, find the current through the 20 ohm resistance in milliamperes.

Explanation

GATE→2022→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q13

MCQ[1 Mark]

For an ideal MOSFET biased in saturation, what is the magnitude of the small-signal current gain for a common-drain amplifier?

(A)

0

(B)

1

(C)

100

(D)

infinite

Explanation

GATE→2022→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q14

MCQ[1 Mark]

For the op-amp circuit with capacitor in feedback and 0.1 V DC input, what is the steady-state output V_out?

(A)

saturate to +V_DD

(B)

saturate to -V_EE

(C)

become equal to 0.1 V

(D)

become equal to -0.1 V

Explanation

GATE→2022→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q15

MCQ[1 Mark]

For the diode bridge/clipper circuit shown with ideal diodes D1 and D2, what is the output V_out?

(A)

V_out = V_in for V_in > 0

(B)

V_out = V_in for V_in < 0

(C)

V_out = -V_in for V_in > 0

(D)

V_out = -V_in for V_in < 0

Explanation

GATE→2022→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q16

MCQ[2 Marks]

How does the output impedance Z_out of a non-ideal op-amp configured as a voltage follower vary with increasing frequency f?

(A)

(A)

(B)

(B)

(C)

(C)

(D)

(D)

Explanation

GATE→2022→Analog and Digital Electronics→Analog Circuits, Op-Amps & Filters

Q17

MCQ[2 Marks]

Find the current gain I_out / I_in for the given switched-capacitor or op-amp current amplifier circuit with capacitors C_f and C_c.

(A)

C_f / C_c

(B)

-C_f / C_c

(C)

C_c / C_f

(D)

-C_c / C_f

Explanation

Digital Logic & Converters

11 Questions

GATE→2026→Analog and Digital Electronics→Digital Logic & Converters

Q18

MCQ[2 Marks]

For the given digital logic circuit with inputs x, y, z, find the simplified Boolean expression for OUT.

(A)

not(x) not(y) not(z)

(B)

0

(C)

not(x)(y + z)

(D)

1

Explanation

GATE→2026→Analog and Digital Electronics→Digital Logic & Converters

Q19

MCQ[2 Marks]

For the MOSFET logic circuit powered at 5 V with resistors 5 kohm and 10 kohm, find OUT expression and maximum power P.

(A)

OUT = AB + not(C), P = 5 mW

(B)

OUT = not((A + B)not(C)), P = 5 mW

(C)

OUT = AB not(C) + not(C), P = 7.5 mW

(D)

OUT = not(A)not(B)C, P = 7.5 mW

Explanation

GATE→2025→Analog and Digital Electronics→Digital Logic & Converters

Q20

MCQ[2 Marks]

Simplify the given Boolean function in Product of Sums (POS) form.

(A)

not(u) and not(w)

(B)

not(u) or not(w)

(C)

not(v) and not(x)

(D)

v or x

Explanation

GATE→2024→Analog and Digital Electronics→Digital Logic & Converters

Q21

MCQ[1 Mark]

Simplify the Boolean function F(P,Q,R,S) = not(P)not(Q) + not(P)QS + P not(Q)not(R)not(S) + P not(Q)R not(S).

(A)

not(P)S + not(Q)not(S)

(B)

not(P)not(Q) + not(Q)not(S)

(C)

not(P)Q + R not(S)

(D)

P not(S) + Q not(R)

Explanation

GATE→2024→Analog and Digital Electronics→Digital Logic & Converters

Q22

MCQ[1 Mark]

With initial Z = 1, X = 1, Y = 0, and S = X XOR Y XOR Z, find S and Z after clock edge.

(A)

S = 0, Z = 0

(B)

S = 0, Z = 1

(C)

S = 1, Z = 0

(D)

S = 1, Z = 1

Explanation

GATE→2024→Analog and Digital Electronics→Digital Logic & Converters

Q23

MCQ[1 Mark]

To implement F(X,Y) = X not(Y) + not(X) using a 4:1 multiplexer with select lines X, Y, what should inputs PQRS be?

(A)

1010

(B)

1110

(C)

1011

(D)

0110

Explanation

GATE→2023→Analog and Digital Electronics→Digital Logic & Converters

Q24

MCQ[2 Marks]

An 8-bit ADC has range 0 to +5 V. For V_in = 1.9922 V, find the corresponding digital output in hexadecimal.

(A)

64H

(B)

65H

(C)

66H

(D)

67H

Explanation

GATE→2023→Analog and Digital Electronics→Digital Logic & Converters

Q25

NAT[2 Marks]

Find the decimal equivalent of the initial binary state [ABCD] that remains unchanged upon clock pulses in the given sequential logic circuit.

Explanation

GATE→2023→Analog and Digital Electronics→Digital Logic & Converters

Q26

NAT[2 Marks]

For microcontroller registers R0 = 0x60 and R1 = 0x46, execute ADD R0, R1 and find the decimal equivalent of flag pattern [CAOP].

Explanation

GATE→2022→Analog and Digital Electronics→Digital Logic & Converters

Q27

NAT[1 Mark]

Cascading a MOD 2 up-counter and a MOD 5 up-counter results in a MOD ... counter.

Explanation

GATE→2022→Analog and Digital Electronics→Digital Logic & Converters

Q28

NAT[1 Mark]

Find the maximum clock frequency in MHz for a 4-stage ripple counter where each flip-flop has a propagation delay of 20 ns.

Explanation